Central Processor Unit (CPU) Registers
Table 4-2. Status Register Bit Definitions (Continued)
Bit Number
9–8
Bit Name
I[1–0]
Reset Value
11
Interrupt Mask
Description
Reflect the current Interrupt Priority Level (IPL) of the processor and
indicate the IPL needed for an interrupt source to interrupt the processor.
The current IPL of the processor can be changed under software control.
The interrupt mask bits are set during hardware reset, but not during
software reset.
7
S
0
Priority
Lowest
Highest
Scaling
I1
0
0
1
1
I0
0
1
0
1
Exceptions
Permitted
IPL 0, 1, 2, 3
IPL 1, 2, 3
IPL 2, 3
IPL 3
Exceptions Masked
None
IPL 0
IPL 0, 1
IPL 0, 1, 2
Set when a result moves from accumulator A or B to the XDB or YDB buses
(during an accumulator to memory or accumulator to register move) and
remains set until explicitly cleared; that is, the S bit is a sticky bit. The
logical equations of this bit are dependent on the Scaling mode. The scaling
bit is set if the absolute value in the accumulator, before scaling, is > 0.25 or
< 0.75.
6
L
0
Limit
Set if the overflow bit is set or if the data shifter/limiter circuits perform a
limiting operation. In Arithmetic Saturation mode, the L bit is also set when
an arithmetic saturation occurs in the Data ALU result; otherwise, it is not
affected. The L bit is cleared only by a processor reset or by an instruction
that specifically clears it (that is, a sticky bit); this allows the L bit to be used
as a latching overflow bit. The L bit is affected by data movement
operations that read the A or B accumulator registers.
5
E
1
Extension
Cleared if all the bits of the integer portion of the 56-bit result are all ones or
all zeros; otherwise, this bit is set. The Scaling mode defines the integer
portion. If the E bit is cleared, then the low-order fraction portion contains all
the significant bits; the high-order integer portion is sign extension. In this
case, the accumulator extension register can be ignored. If the E bit is set, it
indicates that the accumulator extension register is in use.
S1
0
0
1
1
S0
0
1
0
1
Scaling Mode
No scaling
Scale down
Scale up
Reserved
Integer Portion
Bits 55–47
Bits 55–48
Bits 5–46
Undefined
4
U
0
Unnormalized
Set if the two MSBs of the Most Significant Portion (MSP) of the result are
identical; otherwise, this bit is cleared. The MSP portion of the A or B
accumulators is defined by the Scaling mode.
S1
0
0
1
1
S0
0
1
0
1
Scaling Mode
No scaling
Scale down
Scale up
Reserved
Integer Portion
U = (Bit 47 XOR Bit 46)
U = (Bit 48 XOR Bit 47)
U = (Bit 46 XOR Bit 45)
U undefined
DSP56311 User’s Manual, Rev. 2
Freescale Semiconductor
4-9
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